1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a capacitor of a semiconductor device capable of improving capacitance thereof.
2. Description of the Prior Art
Recently, a PSEUDO SRAM combining a DRAM with a SRAM has been developed. In such a PSEUDO SRAM, a capacitor identical to that of the DRAM is adopted in order to form a device. The capacitor stores electric charges, and provides the electric charges required for operating a semiconductor device. As semiconductor devices become highly integrated, a size of one unit cell becomes smaller so that capacitance required for operating the semiconductor devices is gradually increased.
That is, even though there is a demand for reducing a size of the capacitor as the semiconductor devices are highly integrated, there is a limitation on storage of the electric charges in the capacitor, so it is difficult to highly integrate the capacitor to match with a size of a cell. In order to solve the above-mentioned problem, manufacturers have proposed various structures for storing electric charges in the capacitor. For example, in order to increase the electric charges stored in the capacitor, various methods including a method using material having a high dielectric constant, a method reducing a thickness of dielectric material and a method increasing a surface area of the capacitor, have been proposed. Recently, a method increasing the surface area of a capacitor has mainly been used.
In order to increase the surface area of the capacitor, there has been suggested a method of increasing a height of the capacitor by using a PE-TEOS (Plasma Enhanced-Tetra Ethyl Ortho Silicate) layer.
FIG. 1 is a plan view showing a growth of a hemispherical grain formed in a normal cell block when a PE-TEOS layer is not subject to an annealing process.
In an SRAM having a peripheral area larger than a peripheral area of a DRAM, when the hemispherical grain is grown in order to increase the surface area of the capacitor, contaminating materials contained in a PE-TEOS layer, such as carbon, are diffused to an exterior, thereby interrupting growth of the hemispherical grain in the edge and the test pattern of the cell block, in which the PE-TEOS layer is largely distributed. Accordingly, it is difficult to increase the capacitance of the capacitor.
FIG. 2 is a plan view showing a growth of a hemispherical grain in an edge and a test pattern of a cell block when a PE-TEOS layer is not subject to an annealing process. As is understood from FIGS. 1 and 2, a size and a density of the hemispherical grain shown in FIG. 2 are inferior to a size and a density of the hemispherical grain shown in FIG. 1.
Accordingly, in order to solve the problem regarding the size and density of the hemispherical grain as shown in FIG. 2, after the PE-TEOS layer is formed, a storage node contact is formed by etching the PE-TEOS layer by using a hard mask. Then, the annealing process is carried out with respect to the resultant PE-TEOS layer. Thereafter, a storage node electrode filling the storage node contact, a dielectric layer, and a plate electrode are formed, thereby fabricating the capacitor.
If the annealing process is applied to the PE-TEOS layer in the manner as described above, capacitance uniformity is improved than capacitance uniformity obtained without performing the annealing process. Accordingly, mean capacitance is increased by about 2.7 F/cell. However, such a capacitance increase is insufficient when considering the growth of the hemispherical grain. That is, if the annealing process is carried out with respect to the PE-TEOS layer after forming the storage node contact, a shrinkage phenomenon of the PE-TEOS layer may occur so capacitance is insufficiently increased.